Customers may often desire to simulate an IC (integrated circuit) design within the context of a system design that spans across the IC design fabric, the package design fabric, and PCB (printed circuit board) design fabric. The schematics of PCB and Package may not always exist at the time of simulation. Even if the schematics of PCB and Package do exist at the time of simulation, these schematics may be available in different formats for different schematic tools. As a result, these schematics may be incompatible with each other and thus cannot be simulated together without translation, transformation, compilation, etc. (collectively transformation).
In addition, customers may desire to simulate this system design within the context of parasitics of the chip layout, the package layout, and the PCB layout. The parasitic-models may be extracted as combined geometries across multiple design fabrics. Some examples of such models may include on-chip spiral inductor extracted in conjunction with the package planes and traces. In some cases, complete PCB (or package) may be extracted as a single parasitic model that needs to connect to the remainder of the system. Nonetheless, it is very difficult to include parasitics from different design fabrics (e.g., different design fabrics in various layouts) in the multi-fabric schematic.
Conventional approaches require manual creation of parasitic aware multi-fabric schematics where a new schematic is manually created where PCB and package components are stitched into the IC schematic to create the multi-fabric schematic. On the other hand, if PCB/package schematics available in their native schematic editors, user needs to copy the same schematics in the IC schematic entry tool. In some cases, if PCB/package schematics do not exist, user has to construct new schematic by going through respective layouts to obtain the connectivity.
In addition, parasitics of PCB and package traces and metal passive structures are manually stitched into the multi-fabric schematic. Moreover, if parasitic models are extracted from portion of geometry that crosses multiple design fabrics, a user is required to keep a record of model interfaces to ensure that the model is properly connected and stitched into system schematic that spans across the IC design fabric, the PCB design fabric, and the package design fabric to maintain the entire design in single schematic entry tool for purposes of simulations.
Therefore, there exists a need for a method, system, and computer program product for provisioning measurements for constructing a multi-fabric schematic of an electronic design across multiple design fabrics.